(1) Field of the Invention
The present invention relates to semiconductor manufacturing and is more particularly directed to a single-poly EEPROM (electrically erasable programmable read only memory) cell formed with a MIM (Metal-Insulator-Metal) coupling capacitor, and also to a method of forming the same.
(2) Description of the Related Art
It is the preferred practice in the art that, when embedding memory cells into a standard logic process, the single-poly process that is typically used in the fabrication of logic circuitry not be altered. This has led to the development of a single-poly EEPROM cell having N+ source and N+ drain regions formed in a P-substrate and a polysilicon gate overlying a channel region extending between the source and the drain. An N diffusion region formed in the P-substrate serves as the control gate and is capacitevely coupled to the floating gate via a thin oxide layer. The oxide layer has a tunnel window opened in a portion thereof near the N+ drain to facilitate electron tunneling. Since the control gate and floating gate of this single-poly EEPROM cell form a capacitor in a manner similar to that of the more traditional stacked-gate, or double-poly EEPROM cells, the single-poly EEPROM cell is programmed, erased, and read in a manner similar to that of the double-poly EEPROM cell. That is, programming is accomplished by electron tunneling from the floating gate to the substrate, while erasing is realized by electron tunneling from the substrate/drain region to the floating gate. But this N-channel single-poly EEPROM cell requires relative large programming and erasing voltages on the order of 14 volts. These high programming and erase voltages limit the extent to which the size of such cells may be reduced.
Accordingly, workers in the field have devised EEPROM cells which require lower programming voltages. One such cell is a P-channel single-poly flash cell shown in FIG. 1a. The cell is formed in an N-well (12) provided within a P-substrate (10) and includes a P-channel storage transistor (20) and a P-channel select transistor (30), as shown in FIG. 1b. P+ diffusion region (14) serves as the source for storage transistor (20), P+ diffusion region (16) serves as both the drain for storage transistor (20) and the source for select transistor (30), and P+ diffusion region (18), which is coupled to a bit line BL, serves as the drain for select transistor (30). Polysilicon gates (25) and (35) serve as the floating gate and select gate, respectively, of the flash cell as shown in FIG. 1c. Application of a bias voltage to control gate (15) (FIGS. 1a and 1c) enhances channel (17) (FIG. 1b) extending between source (14) and drain (16) of storage transistor (20), and the application of a bias voltage to select gate (35) enhances channel (19) extending between source (16) and drain (18) of select transistor (30).
The P-type buried diffusion layer (15) serves as the control gate of the flash cell of FIG. 1a. A contact (40) is opened in floating gate (25) and in a layer of oxide interposed between floating gate (25) and control gate (15) to enable electrical contact with buried control gate (15). Tunnel oxide layer (50) (FIG. 1b) may extend over channel (17) and substantial portions of source (14) and drain (16). Floating gate (25) together with control gate (15) form an MOS capacitor in the same manner as that of conventional N-channel EEPROM cells. However, the buried junction of control gate (15) of FIG. 1c normally experiences breakdown due to relatively large voltages. It is disclosed later in the embodiments of the present invention an EEPROM cell which is still of single-poly type, but where the buried control gate is replaced by a vertically formed metal-insulator-metal (MIM) coupling capacitor, thereby eliminating the junction breakdown issue and at the same time reducing the cell area by more than 25%.
MIM capacitors are known in the art. In U.S. Pat. No. 5,258,315, Prasad, et al., describe a MIM capacitor formed by sandwiching silicon nitride between a first layer metal and a capacitor top plate using a heterojunction bipolar transistor (HBT) integrated circuit (IC) process. DeKersmaecker, et al., show in U.S. Pat. No. 4,217,601 a non-volatile memory device fabricated from graded or stepped energy band gap insulator MIM or MIS (metal-insulator-silicon) structures.
On the other hand, Lee of U.S. Pat. No. 5,856,688 describes an integrated circuit memory device having nonvolatile single transistor unit cells therein. The memory device includes a gate oxide insulating layer on a surface of a semiconductor substrate containing a bulk region of first conductivity type and spaced source and drain regions of second conductivity type therein extending to the surface. First and second separate control gates are also provided in each unit cell and extend opposite the surface. A ferroelectric insulating layer is provided between the first and second control gates and acts as a nonvolatile data storage medium when it is polarized in a predetermined state. A floating gate is also provided having a C-shape. In this manner, Lee provides an integrated circuit device having a reduced unit cell size.
In the present invention, a memory cell of reduced size is also provided. However, this is accomplished differently by replacing a buried control gate of a single-poly EEPROM device with a vertically formed MIM capacitor, which serves as a control gate over the only polysilicon layer floating gate, thereby also reducing the size of the cell by more than 25%.
It is therefore an object of the present invention to provide a single-poly EEPROM device having a vertically formed metal-insulator-metal (MIM) coupling capacitor, thus with a substantially reduced cell area.
It is another object of the present invention to provide a single-poly EEPROM cell having a vertically formed MIM capacitor which serves as a control gate in place of a buried control gate, thus eliminating the problem of junction breakdown.
It is yet another object of the present invention to provide a single-poly EEPROM cell with increased coupling ratio of the control gate and reduced erase voltage.
It is still another object of the present invention to provide a method of forming a single-poly EEPROM device with a vertically formed MIM capacitor, which serves as a control gate in place of a buried control gate thereby eliminating the problem of junction breakdown and at the same time reducing the size of the cell by more than 25%.
These objects are accomplished by providing a semiconductor substrate having a shallow trench isolation with active region defined; a tunnel oxide covering said semiconductor substrate; an interlevel dielectric (ILD) layer over said tunnel oxide; a floating gate with a window through said ILD reaching underlying said tunnel oxide; a first metal layer over said ILD reaching underlying said floating gate through a via hole; an intermetal dielectric (IMD) layer over said first metal layer; an opening having inside walls in said IMD layer reaching said first metal layer; a capacitor dielectric layer conformally covering said first metal layer and said inside walls of said opening in said IMD layer; and a second metal layer conformally covering said capacitor dielectric layer in said hole, thus forming said MIM coupling capacitor of said EEPROM cell.
The objects are further accomplished by providing a semiconductor substrate having active and passive regions defined; forming shallow trench isolation (STI) in said substrate; forming tunnel oxide layer over said substrate, including said STI; forming an interlevel dielectric (ILD) layer over said tunnel oxide layer; forming a floating gate within said ILD layer and reaching underlying said tunnel oxide layer; forming an intermetal dielectric (IMD) layer over said substrate, including said floating gate; forming an opening in said IMD layer having inside walls in said IMD layer reaching said first metal layer; forming a conformal dielectric layer covering said first metal layer and said inside walls of said opening in said IMD layer; forming a second metal layer conformally covering said capacitor dielectric layer in said hole, thus forming said MIM coupling capacitor of said EEPROM cell.